International Journal of Modern Education and Computer Science (IJMECS)
ISSN: 2075-0161 (Print), ISSN: 2075-017X (Online)
Published By: MECS Press
IJMECS Vol.7, No.3, Mar. 2015
A Novel Quaternary Full Adder Cell Based on Nanotechnology
Full Text (PDF, 501KB), PP.19-25
Binary logic circuits are limited by the requirement of interconnections. A feasible solution is to transmit more information over a signal line and utilizing multiple-valued logic (MVL). This paper presents a novel high performance quaternary full adder cell based on carbon nanotube field effect transistor (CNTFET). The proposed Quaternary full adder is designed in multiple valued voltage mode. CNTFET is a promising candidate for replacing MOSFET with some useful properties, such as the capability of having the desired threshold voltage by regulating the diameters of the nanotubes, which make them very appropriate for voltage mode multiple threshold circuits design. The proposed circuit is examined, using Synopsys HSPICE with the standard 32 nm CNTFET technology with different temperatures and supply voltages.
Cite This Paper
Fazel Sharifi, Mohammad Hossein Moaiyeri, Keivan Navi,"A Novel Quaternary Full Adder Cell Based on Nanotechnology", IJMECS, vol.7, no.3, pp.19-25, 2015.DOI: 10.5815/ijmecs.2015.03.03
A. Raychowdhury and K. Roy, "Carbon nanotube electronics: design of high-performance and low-power digital circuits", Circuits and Systems I: Regular Papers, IEEE Transactions on, Vol. 54, No. 11, pp. 2391-2401, 2007.
S. Sayedsalehi, M. H. Moaiyeri and K. Navi, "Novel Efficient Adder Circuits for Quantum-Dot Cellular Automata", Journal of Computational and Theoretical Nanoscience, Vol. 8, No. 9, pp. 1769-1775, 2011.
M. H. Moaiyeri, A. Doostaregan and K. Navi, "Design of Energy-Efficient and Robust Ternary Circuits for Nanotechnology", IET Circuits, Devices & Systems, Vol. 5, No. 4, pp. 285–296, 2011.
S. Lin , Y. B. Kim and F. Lombardi, "CNTFET-based design of ternary logic gates and arithmetic circuits", Nanotechnology, IEEE Transactions on, Vol. 10, No. 2, pp. 217-225, 2011.
K. Navi, M. H. Moaiyeri, R. Faghih Mirzaee, O. Hashemipour, and B. Mazloom Nezhad, "Two new low-power full adders based on majority-not gates", Elsevier, Microelectronics Journal, Vol. 40, No. 1, pp. 126-130, 2009.
McEuen, P. L. Fuhrer, M. Park, "Single-Walled Carbon Nanotube Electronics", IEEE Transactions on Nanotechnology. pp. 78-85, 2002.
R. Zarhoun, M. H. Moaiyeri, S. S. Farahani and K. Navi, "An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs", ETRI Journal, Vol. 36, No. 1, pp. 89-98, 2014.
Y. B. Kim, F. Lombardi, "Novel design methodology to optimize the speed and power of the CNTFET circuits", Proc IEEE International Midwest Symposium on Circuits and Systems, pp.1130-1133, 2009.
Raychowdhury, K. Roy, "Carbon nanotube electronics: design of high-performance and low-power digital circuits", IEEE Transactions on Circuits and Systems. 54(11). pp. 2391-2401, 2007.
K. Vasundara Patel S, K. S Gurumurthy, "Design of High Performance Quaternary Adders", International Journal of Computer Theory and Engineering, Vol.2, No.6, 2010.
I.M. Thoidis, D. Soudris, J. M. Fernandezl and A. Thanailakis, "THE CIRCUIT DESIGN OF MULTIPLE-VALUED LOGIC VOLTAGE-MODE ADDERS", IEEE International Symposium on Circuits and Systems, 2001.
H. Shirahama, T. Hanyu, "Design of High-Performance Quaternary Adders Based on Output-Generator Sharing", 38th International Symposium on Multiple Valued Logic, 10.1109/ISMVL, 2008.
M. H. Moaiyeri, K. Navi and O. Hashemipour, "Design and Evaluation of CNFET-based Quaternary Circuits", Springer, Circuits, Systems, and Signal Processing, Vol. 31, No. 5, pp. 1631–1652, 2012.
J. Deng, H-S.P. Wong, "Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region", IEEE Transactions on Electron Device. 54, (12). pp. 3186-3194, 2007.
J. Deng, Wong, "A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking". IEEE Transactions on Electron Device. 54 (12). pp. 3195-3205, 2007.
J. Deng, "Device modeling and circuit performance evaluation for nanoscale devices: silicon technology beyond 45 nm node and carbon nanotube field effect transistors," Doctoral Dissertation. Stanford University, 2007.