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International Journal of Modern Education and Computer Science (IJMECS)

ISSN: 2075-0161 (Print), ISSN: 2075-017X (Online)

Published By: MECS Press

IJMECS Vol.10, No.1, Jan. 2018

Design and Analysis of Tunnel FET for Low Power High Performance Applications

Full Text (PDF, 813KB), PP.65-73


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Author(s)

Umesh Dutta, M.K.Soni, Manisha Pattanaik

Index Terms

TFET;Parameter variation;Subthreshold swing;Leakage power;Reliability;Band to Band tunneling;High-K dielectric material;ITRS

Abstract

Tunnel FET is a promising device to replace MOSFET in low power high performance applications. This paper highlights and compares the best TFET designs proposed in the literature namely: Double gate Si-based TFET, InAs TFET device and III-V semiconductor (GaAs1-xSbx-InAs) based TFET device. Simulations are performed using TCAD tool and simulation results suggest that conventional DGTFET device has less on current and degraded subthreshold slope as compared to InAs and III-V semiconductor based TFET device. InAs based TFET device provides steep subthreshold slope of 61 mV/dec and off current of the order of nano-amperes at sub 1V operation thereby making it an ideal choice for low power high performance applications. The variation in the performance of the III-V HTFET device with the variation in the mole fraction is also studied in detail. Carefully choosing the mole fraction value in III-V semiconductor based HTFET device can lead to better device performance.

Cite This Paper

Umesh Dutta, M.K.Soni, Manisha Pattanaik, "Design and Analysis of Tunnel FET for Low Power High Performance Applications", International Journal of Modern Education and Computer Science(IJMECS), Vol.10, No.1, pp. 65-73, 2018.DOI: 10.5815/ijmecs.2018.01.07

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