A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier

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Maryam Mohajer 1,* Mojtaba Valinataj 1

1. School of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Babol, 47148-71167, Iran

* Corresponding author.

DOI: https://doi.org/10.5815/ijmecs.2017.06.03

Received: 6 Feb. 2017 / Revised: 26 Mar. 2017 / Accepted: 25 Apr. 2017 / Published: 8 Jun. 2017

Index Terms

Fault-tolerance, Reduced precision, Floating-point multiplier, Error detection, Error correction


This paper presents a new fault-tolerant architecture for floating-point multipliers in which the fault-tolerance capability is achieved at the cost of output precision reduction. In this approach, to achieve the fault-tolerant floating-point multiplier, the hardware cost of the primary design is reduced by output precision reduction. Then, the appropriate redundancy is utilized to provide error detection/correction in such a way that the overall required hardware becomes almost the same as the primary multiplier. The proposed multiplier can tolerate a variety of permanent and transient faults regarding the acceptable reduced precisions in many applications. The implementation results reveal that the 17-bit and 14-bit mantissas are enough to obtain a floating-point multiplier with error detection or error correction, respectively, instead of the 23-bit mantissa in the IEEE-754 standard-based multiplier with a few percent area and power overheads.

Cite This Paper

Maryam Mohajer, Mojtaba Valinataj, "A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier", International Journal of Modern Education and Computer Science(IJMECS), Vol.9, No.6, pp.17-24, 2017. DOI:10.5815/ijmecs.2017.06.03


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