A Review of NBTI Degradation and its Impact on the Performance of SRAM

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Umesh Dutta 1,* M.K Soni 1 Manisha Pattanaik 2

1. Department of Electronics and Communication Engineering, FET, MRIU Faridabad, Haryana, India

2. ICT Faculty, ABV-IIITM Gwalior, Madhya Pradesh, India

* Corresponding author.

DOI: https://doi.org/10.5815/ijmecs.2016.06.08

Received: 2 Mar. 2016 / Revised: 2 Apr. 2016 / Accepted: 10 May 2016 / Published: 8 Jun. 2016

Index Terms

NBTI, Positive Bias Temperature Instability (PBTI), Static Noise Margin (SNM), Hot Carrier Injection (HCI), Reliability, Threshold Voltage, RD model, SRAM, Genetic Algorithm (GA), Body Bias (BB), Yield


Temporal degradation of VLSI design is a major reliability concern for highly scaled silicon IC technology. Negative Bias Temperature Instability (NBTI) in particular is a serious threat affecting the performance of both digital and analog circuits with time. This paper presents a review of NBTI degradation, its mechanism and various factors that affect the degradation caused by NBTI. Reaction Diffusion (RD) model based analytical expressions developed by various researchers are also discussed along with their features and underlying assumptions. Degradation in the Static RAM (SRAM) performance caused by NBTI is also discussed in detail along with the strategies that are employed to combat the effect of NBTI degradation in SRAM. Results of the review done for SRAM cell under NBTI degradation suggests that these design strategies are effective in improving the SRAM cell performance.

Cite This Paper

Umesh Dutta, M.K Soni, Manisha Pattanaik, "A Review of NBTI Degradation and its Impact on the Performance of SRAM", International Journal of Modern Education and Computer Science(IJMECS), Vol.8, No.6, pp.57-65, 2016. DOI:10.5815/ijmecs.2016.06.08


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