Element-Based Computational Model

Full Text (PDF, 593KB), PP.1-11

Views: 0 Downloads: 0


Conrad Mueller 1,*

1. School of Electrical and Information Engineering, The University of the Witwatersrand and School of IT Monash South Africa, Johannesburg

* Corresponding author.

DOI: https://doi.org/10.5815/ijmecs.2012.01.01

Received: 10 Sep. 2011 / Revised: 3 Oct. 2011 / Accepted: 2 Dec. 2011 / Published: 8 Jan. 2012

Index Terms

Computational Model, Data-Flow, Computer Architecture, Parallel Architecture.


A variation on the data-flow model is proposed to use for developing parallel architectures. While the model is a data driven model it has significant differences to the data- flow model. The proposed model has an evaluation cycle of processing elements (encapsulated data) that is similar to the instruction cycle of the von Neumann model. The elements contain the information required to process them. The model is inherently parallel. An emulation of the model has been implemented. The objective of this paper is to motivate support for taking the research further. Using matrix multiplication as a case study, the element/data-flow based model is compared with the instruction-based model. This is done using complexity analysis followed by empirical testing to verify this analysis. The positive results are given as motivation for the research to be taken to the next stage - that is, implementing the model using FPGAs.

Cite This Paper

Conrad Mueller, "Element-Based Computational Model", International Journal of Modern Education and Computer Science (IJMECS), vol.4, no.1, pp.1-11, 2012. DOI:10.5815/ijmecs.2012.01.01


[1]John L. Hennessy David A. Patterson, “Computer Organization and Design: The Hardware/Software Interface”, Morgan Kaufmann, 4th edition, (2009).
[2]Kreste Asanovic, Ras Bodik, Bryan Christopher Catanzaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David P. Patterson, William Lester Plishker, John Shalf, Samuel Webb Wiliams, and Katherine A. Yelick, “The landscape of parallel computing research: A view from Berkeley”, Technical report, Electrical Engineering and Computer Sciences, University of California at Berkeley, (2006).
[3]Klaus Erik Schauser David E. Culler and Thorsten von Eicken, “Two fundamental limits on dataflow multiprocessing”, Technical Report UCB/CSD-92-716, EECS Department, University of California, Berkeley, (1992).
[4]David Patterson John Hennessy, “A conversation with John Hennessy and David Patterson”, ACM Queue, 4(10), 2006.
[5]http://www.mpi forum.org/. Message passing interface forum.
[6]Arvind, “Data flow languages and architectures”, ISCA '81: Proceedings of the 8th annual symposium on Computer Architecture, 1981.
[7]Sajjan G Shivas, Advanced Computer Architecture, pages 284-299, 2006.
[8]R.S.V. Whiting, P.G. Pascoe, “A history of data- flow languages”, Annals of the History of Computing, IEEE.
[9]J. Teifel and R. Manohar, “An asynchronous dataflow fpg a architecture”, Computers, IEEE Transactions on, 53(11):1376–1392, Nov. 2004.