An Approximate 4-2 Compressor based on Spintronic Devices

Full Text (PDF, 913KB), PP.35-41

Views: 0 Downloads: 0


Mohammad Ali Shafieabadi 1,* Fazel Sharifi 1 Mohammad Mehdi Faghih 1

1. Department of Electrical and Computer Engineering, Graduate University of Advanced Technology, Kerman, Iran

* Corresponding author.


Received: 27 May 2019 / Revised: 23 Jun. 2019 / Accepted: 1 Jul. 2019 / Published: 8 Aug. 2019

Index Terms

Approximate computing, 4-2 compressor, Multiplier, spintronic technology, Low Power Design


In many classes of applications, mainly in signal and image processing applications, decreasing the static power of computational circuits is a challenge. Multipliers are typically located on the critical path of such systems. A promising approach for energy-efficient design of digital systems is approximate or inexact computing. On the other hand, leakage power and limited scalability become serious obstacles that prevent the continuous miniaturization of the conventional CMOS-based logic circuits. Spin-based devices are considered as promising alternatives for CMOS technology due to their proper characteristics such as near-zero current leakage, sustainability, integrity, low standby power. In this paper a new low power approximate 4-2 compressor is presented which is implemented using spintronic devices. The proposed design is utilized in a multiplier tree for image processing applications. We have simulated and compared the proposed design with state-of-the-art designs in both quantitative and qualitative metrics. The simulation results show that the proposed design has 92% and 188% lower power consumption and PDP, respectively compared to the best state-of-the-art design.

Cite This Paper

Mohammad Ali Shafieabadi, Fazel Sharifi, Mohammad Mehdi Faghih, " An Approximate 4-2 Compressor based on Spintronic Devices", International Journal of Modern Education and Computer Science(IJMECS), Vol.11, No.8, pp. 35-41, 2019.DOI: 10.5815/ijmecs.2019.08.04


[1]Gautschi, “Design of energy-efficient processing elements for near-threshold parallel computing,” 2017, ETH Zurich.
[2]M. Gautschi, and et al., “Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017. 25(10): p. 2700-2713.
[3]W. Liu, S. Fan, A. Khalid, C. Rafferty, and M. O'Neill, “Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA,“ IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019.
[4]S. Hsiao, M. Jiang, and J. Yeh, “Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers,” Electronics Letters, 1998. 34(4): p. 341-343.
[5]A. Arasteh, M. Moaiyeri, M. Taheri, K. Navi, and N. Bagherzaseh, “An energy and area efficient 4: 2 compressor based on FinFETs,” Integration, 2018. 60: p. 224-231.
[6]C. Chang, J. Gu , and M. Zhang, “Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2004. 51(10): p. 1985-1997.
[7]S. Angizi, H. Jiang, R. F.DeMara, J. Han, D. Fan, “Majority-based spin-CMOS primitives for approximate computing,” IEEE Transactions on Nanotechnology, 2018. 17(4): p. 795-806.
[8]D. Balobas and N. Konofaos, “Low-power high-performance CMOS 5-2 compressor with 58 transistors,” Electronics Letters, 2018. 54(5): p. 278-280.
[9]S. Agarwal, G. Harish, S. Balamurugan, and R. Marimuthu ,”Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic,” in International Symposium on VLSI Design and Test. 2018. Springer.
[10]P. Nejadzadeh, and M.R. Reshadinezhad, “Design of an Efficient Current Mode Full-Adder Applying Carbon Nanotube Technology,” International Journal of Modern Education and Computer Science, vol. 10, p. 43, 2018.
[11]F. Sharifi, and H. Thapliyal, “Energy-efficient magnetic circuits based on nanoelectronic devices,” in 2017 IEEE International Symposium on Circuits and Systems (ISCAS). 2017. IEEE.
[12]H. Thapliyal, F. Sharifi, and S.D. Kumar, ” Energy-efficient design of hybrid MTJ/CMOS and MTJ/nanoelectronics circuits,” IEEE Transactions on Magnetics, 2018. 54(7): p. 1-8.
[13]E.Raymenants , and et al, “Scaled spintronic logic device based on domain wall motion in magnetically interconnected tunnel junctions,” In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 36-4). IEEE.
[14]S. Angizi, Z. He, R. F.DeMara, and D. Fan, ” Composite spintronic accuracy-configurable adder for low power digital signal processing,” 18th International Symposium on Quality Electronic Design (ISQED). 2017. IEEE.
[15]X. Fong, and et al., ” Spin-transfer torque devices for logic and memory: Prospects and perspectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015. 35(1): p. 1-22.
[16]D. Zhang, and et al., “Reliability-enhanced hybrid CMOS/MTJ logic circuit architecture,” IEEE Transactions on Magnetics, 2017. 53(11): p. 1-5.
[17]H. Honjo, and et al., “Critical role of W insertion layer sputtering condition for reference layer on magnetic and transport properties of perpendicular-anisotropy magnetic tunnel junction,” IEEE Transactions on Magnetics, 2019.
[18]S. Fukami, and et al, ”20-nm magnetic domain wall motion memory with ultralow-power operation,” IEEE International Electron Devices Meeting. 2013.
[19]J. Liang, J. Han, and F. Lombardi, “New metrics for the reliability of approximate and probabilistic adders,” IEEE Transactions on computers, 2012. 62(9): p. 1760-1771.