Hardware Design and Simulation of Sobel Edge Detection Algorithm

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Sohag Kabir 1,* A S M Ashraful Alam 2

1. Department of Computer Science, University of Hull, Hull, UK

2. Department of Immigration & Passports, Ministry of Home Affairs, Dhaka, Bangladesh

* Corresponding author.

DOI: https://doi.org/10.5815/ijigsp.2014.05.02

Received: 14 Dec. 2013 / Revised: 31 Jan. 2014 / Accepted: 5 Mar. 2014 / Published: 8 Apr. 2014

Index Terms

Edge detection, Sobel Edge detection, Image Processing, FPGA, Hardware Design, Simulation


In this paper, a hardware system for Sobel Edge Detection Algorithm is designed and simulated for a 128 pixel, 8-bit monochrome line-scan camera. The system is designed to detect objects as they move along a conveyor belt in a manufacturing environment, the camera will observe dark objects on a light conveyor belt. The edge detector is required to detect horizontal and vertical edges using Sobel edge detection method. The Sobel operator requires 3 lines and takes 3 pixels per line, thus using a 3×3 input block to process each pixel. The centre pixel of the 3×3 pixel block can be classified as an edge point or otherwise by thresholding the value from the operator. The FPGA based Sobel edge detector is designed and simulated using Altera Quartus II 8.1 web edition by targeting Cyclone II development boards.

Cite This Paper

Sohag Kabir, A S M Ashraful Alam,"Hardware Design and Simulation of Sobel Edge Detection Algorithm", IJIGSP, vol.6, no.5, pp.10-18 , 2014. DOI: 10.5815/ijigsp.2014.05.02


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