A New Adder Theory Based on Half Adder and Implementation in CMOS Gates

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Zhanfeng Zhang 1,* Liyuan Sheng 1 Wenming Jiang 1 Shuai Tong 1 Hua Cao 1

1. School of Physics Science and Technology,Central South University, Changsha, China

* Corresponding author.

DOI: https://doi.org/10.5815/ijigsp.2010.02.02

Received: 28 Aug. 2010 / Revised: 5 Oct. 2010 / Accepted: 10 Nov. 2010 / Published: 8 Dec. 2010

Index Terms

Half adder trigger, parallel feedback carry adder, CMOS gate


This paper proposes a new theory of adder and its basic structure. The new adder of asynchronous structure constructed by half adders, called Parallel Feedback Carry Adder (PFCA) as its carry mode is parallel feedback. In theory, the area consumption of n-bit PFCA is close to O(n) and the average length of carry chain is O(log n). A CMOS gate implementation scheme is implemented. HSPICE simulation results show that PFCA has obvious advantages over RCA, CLA, CSeA in speed and area, especially when n is bigger.

Cite This Paper

Zhanfeng Zhang,Liyuan Sheng,Wenming Jiang,Shuai Tong,Hua Cao, "A New Adder Theory Based on Half Adder and Implementation in CMOS Gates", IJIGSP, vol.2, no.2, pp.11-17, 2010. DOI: 10.5815/ijigsp.2010.02.02


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