Optimized Low Power Dual Edge Triggered Flip-flop with Speed Enhancement

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Shilpa K.C 1,* Lakshminarayana C 2

1. Dr. Ambedkar Institute of Technology, Bengaluru, India

2. B.M.S.College of Engineering, Bengaluru, India

* Corresponding author.

DOI: https://doi.org/10.5815/ijigsp.2022.01.05

Received: 5 Sep. 2021 / Revised: 15 Oct. 2021 / Accepted: 6 Nov. 2021 / Published: 8 Feb. 2022

Index Terms

Dual Edge Triggered (DET), DETFFs (double-edge-triggered flip-flops), Dual Edge Triggered Static Pulsed flip-flop (DETSPFF), Static output Controlled Discharge Flip-flop (SCDFF), FF (Flip-Flop), Single Edge Triggered (SET), Sense Amplifier (SA), VLSI


This paper gives a novel low-power approach with pulse generating circuits using dual edge triggered flip-flops. By doing so, flip-flop might operate at 1.2Volts, with the novel quick latch and conditional precharging. This paper aims at a new proposed low power dual edge triggered flip-flop with speed enhancement to achieve low power consumption with a shorter delay in power usage, hence, it is well suited for low-power digital system applications. The new proposed low power dual edge triggered flip-flop also aims at comparison with the three DETFF, Static Output Controlled Discharge Flip-Flop (SCDFF), Dual Edge Triggered Static Pulsed Flip-flop (DETSPFF), and Pervious work on Dual Edge Triggered flip-flop, proves to achieves with reduction in numbers of transistors in the stack and increases the number of charge-paths results in a faster operational speed. According to simulation on Spectre simulator, it has been observed that total power consumption of proposed flip flop at 0.67 switching activity is 30.16 % and 27.36 % less than that of previous arts DSPFF and SCDFF respectively. Clock-gated sense-amplifier is incorporated to reduce power consumption at low switching activity. The simulation is done using Cadence tool with 45nm standard CMOS technology.

Cite This Paper

Shilpa K.C, Lakshminarayana C, " Optimized Low Power Dual Edge Triggered Flip-flop with Speed Enhancement", International Journal of Image, Graphics and Signal Processing(IJIGSP), Vol.14, No.1, pp. 50-63, 2022. DOI: 10.5815/ijigsp.2022.01.05


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