Design and Implementation of a Novel Complete Filter for EEG Application on FPGA

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Atik Mahabub 1,*

1. Department of Electronics and Communication Engineering, Khulna University of Engineering & Technology, KUET, Khulna, Bangladesh

* Corresponding author.


Received: 8 Mar. 2018 / Revised: 11 Apr. 2018 / Accepted: 11 May 2018 / Published: 8 Jun. 2018

Index Terms

Filter, FPGA, RTL, Floor plan, EEG signal, Timing diagram


Filter is vastly used to detect different human signal in real time. In this paper, a novel complete digital filter is proposed for the fast detection of EEG signals due to avoid the mixtures of different biomedical signals. This paper intends to design a digital complete filter based on Field Programmable Gate Array (FPGA) for the alleviation of unwanted frequency components in biomedical signals specially EEG signals. For this purpose, complete filter which is a combination of integrator filter and differentiator filter which supports both low and high noises and comparatively inexpensive than other signal processing methodologies can be used. For hardware implementation, FPGA board is used which is a combination of different logic gates which offers inexpensive and long lasting services.

Cite This Paper

Atik Mahabub, " Design and Implementation of a Novel Complete Filter for EEG Application on FPGA ", International Journal of Image, Graphics and Signal Processing(IJIGSP), Vol.10, No.6, pp. 22-30, 2018. DOI: 10.5815/ijigsp.2018.06.03


[1]V. Vujičić, S. Milovančev, M. Pešaljević, D. Pejić and I. Župunski, "Low frequency stochastic true RMS instrument," IEEE Trans. Instrum. Meas., vol. 48, pp.467-470, Apr. 1999.

[2]V. Vujičić, “Generalized low frequency stochastic true RMS instrument”, IEEE Trans. Instrum. Meas., vol. 50, pp. 1089-1092, Oct. 2001.

[3]V. Pjevalica, and V. Vujičić, “Further Generalization of the LowFrequency True-RMS instrument”, IEEE Trans. Instrum. Meas., Revised IM 5499, to be published 

[4]Wei-Chung Huang1, Shao-Hang Hung1, Jen-Feng Chung1,2, Meng-Hsiu Chang1, Lan-Da Van2, and Chin-Teng Lin, " FPGA Implementation of 4-Channel ICA for On-line EEG Signal Separation". 

[5]K. K. Shyu, P. L. Lee, M. H. Lee, M. H. L. R. J. Lai, and Y. J. Chiu, “Development of a low-cost FPGA-based SSVEP BCI multimedia control system,” IEEE Trans. Biomed. Circuits Syst., vol. 4, pp. 125–132, April 2010. 

[6]L.P Wijesinghe*, D.S Wickramasuriya, and Ajith A. Pasqual," A Generalized Preprocessing and Feature Extraction Platform for Scalp EEG Signals on FPGA" 

[7]J. Kwong and A. Chandrakasan, “An energy-efficient biomedical signal processing platform,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1742–1753, 2011. 

[8]N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A. Chandrakasan, “A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 804–816, 2010

[9]C. Chou, S. Mohanakrishnan, and J. B. Evans, “FPGA Implementation of Digital Filters”, Proc. Int. Conf. Signal Proc. Appl. & Tech. (ICSPAT’93),1993. 

[10]J. B. Evans, "Efficient FIR filter architectures suitable for FPGA implementation,"IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 41, no. 7, pp. 490-493, Jul 1994.

[11]K. Sundaram, M. Pradeepa, "FPGA based filters for EEG preprocessing," 2016 Second International Conference on Science Technology Engineering and Management (ICONSTEM), Chennai, 2016, pp.572-576.

[12]Frank Vahid (2010). Digital Design with RTL Design, Verilog and VHDL (2nd ed.). John Wiley and Sons. p. 247. ISBN 978-0-470-53108-2.

[13]Md. Nazmul Hasan, Md. Tariq Hasan, Rafia Nishat Toma, Md. Maniruzzaman “FPGA Implementation of LBlock Lightweight Block Cipher” Electrical Engineering and Information Communication Technology (ICEEICT), 2016 3rd International Conference on 22-24 Sept. 2016, Dhaka, Bangladesh.

[14]Shumit Saha, Md. Jahiruzzaman, Chandan Saha, Md. Rubel Hosen, Atiq Mahmud “FPGA Implementation of Modified Type-C PID Control System” in 2nd Int'l Conf on Electrical Engineering and Information & Communication Technology (ICEEICT) 2015 Jahangirnagar University, Dhaka-1342, Bangladesh, 21-23 May 2015.