Design of Low Power Test Pattern Generator using Low Transition LFSR for high Fault Coverage Analysis

Full Text (PDF, 337KB), PP.15-21

Views: 0 Downloads: 0


Chethan J 1,* Manjunath Lakkannavar 1

1. VTU Extension Center, UTL Technologies Ltd, Visvesvaraya Technological University, Bengaluru, Karnataka, India

* Corresponding author.


Received: 10 May 2013 / Revised: 6 Jun. 2013 / Accepted: 1 Jul. 2013 / Published: 8 Aug. 2013

Index Terms



A low power Test Pattern Generator (TPG) designed by modifying Linear Feedback Shift Register is proposed to produce low power test vectors that are deployed on Circuit under Test (CUT) to slenderize the dynamic power consumption by CUT. The technique involved in generating low power test patterns is performed by increasing the correlativity between the successive vectors; the ambiguity in increasing the similarity between consecutive vectors is resolved by reducing the number of bit flips between successive test patterns. Upon deploying the low power test patterns at the inputs of CUT, slenderizes the switching activities inside CUT that in turn reduces its dynamic power consumption. The resulted low power test vectors are deployed on CUT to obtain fault coverage. The experimental results demonstrate significant power reduction by low power TPG than compared to standard LFSR.

Cite This Paper

Chethan J, Manjunath Lakkannavar, "Design of Low Power Test Pattern Generator using Low Transition LFSR for high Fault Coverage Analysis", International Journal of Information Engineering and Electronic Business(IJIEEB), vol.5, no.2, pp.15-21, 2013. DOI:10.5815/ijieeb.2013.02.03


[1]Sakthivel, P., A. NirmalKumar and T. Mayilsamy “Low Transition Test Pattern Generator Architecture for Built in Self Test,” American Journal of Applied Sciences 9 (9): 1396-1406, ISSN 1546-9239, 2012.

[2]Sabir Hussain1 K Padma Priya, “Test Pattern Generator (TPG) for Low Power Logic Built In Self Test (BIST)” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 2, Issue 4, April 2013.

[3]S. Kundu and S. Chattopadhyay, “Embedding a Low Power Test Set for Deterministic BIST using a Gray Counter”, Proceedings of the World Congress on Engineering, London, U.K, Vol II, July 6 - 8, 2011.

[4]Pradhan, D.K and C. Liu, 2005. EBIST: A novel test generator with built in fault detection capability. IEEE Trans. Comput. Aided Design Integrated Circ. Syst., 24: 1457-1466. DOI 10.1109/TCAD.2005.850815.

[5]K Vasudevareddy, K.V.Ramanaiah and K.Saravani, “Low Power and High Fault Coverage BIST TPG”, IOSR Journal of Engineering (IOSRJEN), e-ISSN: 2250-3021, p-ISSN: 2278-8719, Vol. 3, Issue 5, May 2013.

[6]Dr.R.Varatharajan and Lekha R, “A Low Power BIST TPG for High Fault Coverage”, Information Engineering and Electronic Business, MECS, 4, 19-24, 2012, DOI: 10.5815/ijieeb.2012.04.03.

[7]R. Madhusudhanan and R.Balarani, “A BIST TPG for Low Power Dissipation and High Fault Coverage”, International journal of mc square scientific research, Vol 1 , June 2009.

[8]A. Hertwing and H. J.Wunderlich, “Low Power Serial Built-In Self-Test,” in Proc. European Test Workshop (ETW’98), pp. 49-53, 1998. 

[9]S. Wang, “Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST,” in Proc. Int. Test Conf. (ITC’02), pp. 834 - 843, 2002. 

[10]N. Basturkmen, S. Reddy and I. Pomeranz, “A Low power Pseudo Random BIST Technique,” in Proc. Int. Conf. on Computer Design (ICCD’02), pp. 468-473, 2002. 

[11]K. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain and J. Lewis, “Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques,” in Proc. Int. Test Conf. (ITC’04), pp. 355-364, 2004.

[12]T. Yoshida and M. Watati, “A New Approach for Low Power Scan Testing,” in Proc. Int. Test Conf. (ITC’03), pp. 480-487, 2003. 

[13]F. Corno, M. Rebaudengo, M. Reorda, G. Squillero and M. Violante, “Low Power BIST via Non-Linear Hybrid Cellular Automata,” in Proc. VLSI Test Symp. (VTS’00), pp. 29-34, 2000. 

[14]P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, H. J. Wunderlich, “A modified Clock Scheme for a Low Power BIST Test Pattern Generator,” in Proc. VLSI Test Symp. (VTS’01), pp. 306-311, 2001. 

[15]D. Gizopoulos et. al., “Low Power/Energy BIST Scheme for Datapaths,” in Proc. VLSI Test Symp. (VTS’00), pp. 23-28, 2000. 

[16]X. Zhang, K. Roy and S. Bhawmik, “POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing,” in Proc. Int. Conf. VLSI Design, pp. 416-422, 1999.